1) Field of the Invention
This invention relates to semiconductor devices and more particularly to an improved structure and method for producing electrically programmable read only memory devices (EPROM's) and electrically erasable programmable read only memory devices (EEPROM's).
2) Description of the Prior Art
Computer memories represent one of the fastest growing markets in the world today. Also, computer memory technology is rapidly changing to meet marketplace demands. One of the most important types of computer memory, called an electrically alterable/erasable read only memory (EAROM/EEROM), has a permanent but reprogrammable memory.
Market demands that memories must be faster, smaller and easier to manufacture. In particular there is a challenge to develop stacked gate flash electrically erasable programmable read only memories (EEPROM's or E.sup.2 ROM's) with faster erasure speeds without decreasing the device manufacturing yield.
A conventional EEPROM device works as follows. FIG. 1 shows the conventional stacked gate EEPROM programmed transistor. The stacked EEPROM transistor has an additional polysilicon layer added to the conventional complementary metal oxide semiconductor (CMOS) transistor. This additional polysilicon layer is called a floating gate 16. A control gate 20 is placed above the floating gate 16. The floating gate 16 gets its name because it is not attached to a line but "floats" and is controlled by the control gate 20, source 14 and drain 16 voltages. A thin oxide, called the tunnel oxide 22, separates the floating gate 16 from the source 14, and drain 12 voltages. Another thin insulating layer 18 separates the control gate 20 from the floating gate 16. By controlling the control gate, source and drain voltages, the thin tunnel oxide 22 is used to allow electrons to "tunnel" to or from the floating gate 16 to turn the cell off or on respectively. This tunneling mechanism is called Fowler-Nordheim tunneling. Also, by setting the appropriate voltages on the terminals, "hot electrons" can be induced to charge the floating gate 16, thereby programming the transistor.
Still referring to FIG. 1, a memory cell can be programmed by causing hot electrons to be injected from the drain 12 through gate oxide layer 22 onto the floating gate 16. This injection of electrons occurs under the influence of a relatively strong electrical field. Once the strong electrical field has been removed, these electrons are trapped on floating gate 16 causing the memory cell to be programmed. Accordingly, the memory cell may be programmed by placing a memory cell transistor source 14, such as one of bit lines, at a zero volt potential while placing control gate 20 at a relative high positive voltage potential and pulsing a memory cell transistor drain 12, such as bit line with a relatively high voltage. This process causes the floating gate 16 to become charged or programmed.
A memory cell may be read by placing a memory cell transistor source 14 at a zero volt potential, a memory cell transistor drain 12 at a relatively low positive voltage. If the memory cell has not been previously programmed, then the memory cell conducts current. However, if the memory cell has been previously programmed, floating gate 16 will prevent the memory cell from conducting.
In the conventional floating gate cell structure, the erase operation speed is limited by the electric field strength between source and the floating gate which is limited by the tunnel oxide thickness. The thinner the tunnel oxide thickness the faster the electrons can "tunnel" thorough it. This is because the thinner the tunnel oxide the stronger the electric field between the floating gate and the source or drain. However, as the tunnel oxide is thinned, oxide pin holes cause reliability problems. In practice, the tunnel oxide thickness is formed at the lowest thickness to ensure acceptable reliability and manufacturing yields. This tradeoff between tunnel oxide thickness and erase speed limits the overall speed of conventional EEPROM devices.
A method for fabricating a MOS field effect transistor with a recessed gate with self-aligning source and drain regions is shown in U.S. Pat. No. 5,108,937. The erasure rate for this device is still limited by the tunnel oxide thickness.
A new erasing method for a simple stacked gate flash EEPROM is describe in Yamada et all, "A Self-Convergence Erasing Scheme For a Simple Stacked Gate Flash EEPROM", IEDM 91 pp. 307-310. This publication explains a technique to improve cell erasure. Standard cell erasure is achieved by electron tunneling (Fowler-Nordheim or F-N tunneling) between the floating gate and the drain. Yamada's technique makes use of avalanche hot carrier injection after cell erasure by Fowler-Nordheim (F-N) tunneling. A steady state is caused by a balance between the avalanche hot electron injection into the floating gate and the avalanche hot hole injection into the floating gate. This steady state can be controlled by the channel doping level. This new technique results in a tighter distribution of erase threshold voltages. It also allows pre-programming and iteration of the erase and verify sequence to be eliminated. However, the erase step speed is still limited by the the tunnel oxide thickness and the electric field strength between the floating gate and the source.